岗位职责
??Work closely with the software, hardware and IP team to plan the chip clock architecture and low power proposal.
?? Define chip low power scenario and the related condition.
??Write and validate the CPF/UPF file for chip power description
??Define and develop the verification cases for chip low power design with the verification team.
??Provide the sample code to software team for low power integration.
??Provide the clock SDC for synthesis team.
??Power estimation before chip TO, power breakdown and analysis after chip back.
??Script development for chip low power related automation.
??Interact with external IP teams/vendors to resolve all technical implementation and integration issues.
??Work closely with STA team and PD to for timing closure
任职资格
??MS/BS in EE/CS (MS preferred).
??Minimum 5 years of experience with MSEE/CS or 7 years with BSEE/CS.
??Familiar with ASIC development, especially logic design,? RTL coding, verification, synthesis, timing closure and physical design flow
??Proficient in advanced SOC low power design techniques, hands-on? clock and? PMU design, integration, verification, CPF/UPF script development.
??One or more advantages of the followings are highly desirable: Strong background in synthesis, scan and memory BIST; analog IP design and test, especially high speed Serdes test such as (MIPI, LVDS, USB3.0…; digital communication, CPU and networking protocols; Experiences with ARM/DSP, AHB/AXI bus, NoC and peripheral (PCIe/USB) development.
??Excellent teamwork, interpersonal and communication skills.
??Fluent in Chinese and English both verbal and written.
??Scripting/programming skill in C/C++, Tcl, Perl/Csh desired.
??Ability to work in stressful situations with tight schedules to meet.

工作地点
北京/上海
任职资格
??MS/BS in EE/CS (MS preferred).
??Minimum 5 years of experience with MSEE/CS or 7 years with BSEE/CS.
??Familiar with ASIC development, especially logic design,? RTL coding, verification, synthesis, timing closure and physical design flow
??Proficient in advanced SOC low power design techniques, hands-on? clock and? PMU design, integration, verification, CPF/UPF script development.
??One or more advantages of the followings are highly desirable: Strong background in synthesis, scan and memory BIST; analog IP design and test, especially high speed Serdes test such as (MIPI, LVDS, USB3.0…; digital communication, CPU and networking protocols; Experiences with ARM/DSP, AHB/AXI bus, NoC and peripheral (PCIe/USB) development.
??Excellent teamwork, interpersonal and communication skills.
??Fluent in Chinese and English both verbal and written.
??Scripting/programming skill in C/C++, Tcl, Perl/Csh desired.
??Ability to work in stressful situations with tight schedules to meet.